The invention relates to a current source circuit having a first, second, third and fourth field effect transistor, where the first and second field effect transistors are of a first channel type and the third and fourth field effect transistors of a second channel type and the series-connected channel sections of the first and fourth field effect transistors and of the second and third field effect transistors form a first and second main current path respectively, where the control electrodes of the first and third field effect transistors are connected respectively to the first main current path and the control electrode of the second field effect transistor, and to the second main current path and the control electrode of the fourth field effect transistor in order to form a first and second current mirror respectively, and where a fifth field effect transistor is controlled by the first current mirror to tap a first source current.
A current source circuit of this type is known from the periodical "IEEE Journal of Solid State Circuits", June 1977, pages 224 to 231, particularly FIG. 8 on page 228. This circuit is shown in FIG. 1, where the field effect transistors T1 to T4 combine with the resistor R1 to form a reference current source. Here, the two n-channel transistors T1 and T2 represent a first current mirror. The two p-channel transistors T3 and T4 form in addition a second current mirror.
For the first current mirror "T1, T2", the following applies: ##EQU1## where W/L [.multidot.] state the channel width/channel length ratios of transistors T1 and T2 respectively. Identical transistor sizes for T1 and T2 result in identical current i2 and i1.
For further analysis and for sake of simplicity, i2 is considered to be equal to i1. However, the principle of operation will be maintained even if i2 is bigger or smaller than i1.
For the current i1 in connection with the second current mirror "T3, T4", the value is obtained using the following formula: ##EQU2## where K states the Boltzmann's constant, T the absolute temperature and q the electron charge. With a resistance of R1=M.OMEGA. and a W/L ratio of 8 for the two transistors T4 and T3, the result at a room temperature of 300.degree. K. is a current i1 of 5.4.multidot.10.sup.-8 A.
The above equation (2) applies as long as the two transistors T3 and T4 are in the weak inversion range. This equation also shows that the current i1 has at room temperature a positive temperature coefficient of approx. +3000 ppm/K. when the resistor R1 is assumed to be constant and temperature-independent. For the resistor R1, a p-well resistor is mostly used that has a positive temperature curve. The result for the current i1 is typically a negative temperature coefficient in the range of approx. -5000 to -15000 ppm/K.
In accordance with FIG. 1, a current i3 is tapped via an n-channel field effect transistor T5 of the reference current source, said current being-depending on the selected size ratio of the first current mirror (W/L [T5]/W/L [T1]-a fraction or a multiple of the current i1, with the current i3 naturally having the same temperature dependence as current i1.
As shown above, the current i1 is 54 nA with the stated circuit dimensions. However, since current i2 and i1 are identical, this reference current source according to FIG. 1 itself already consumes a current of approx. 0.1 .mu.A. This current input is however too high for many applications.
One possibility of reducing the current consumption of this known reference current source is to reduce the W/L ratio of the two transistors T4 and T3. This reduces the voltage drop across the resistor R1 and hence, with a given resistance R1, also the current consumption of the circuit. However, this option is tightly circumscribed because very high percentage dispersions of the voltage drop occur at this resistor R1 and hence for the current i1 too when the W/L ratio of the transistors T4 and T3 is very low.
A further possibility is to increase the resistance of R1 to, for example, 10 M.OMEGA., as a result of which the current input of the reference current source drops to around 10 nA, which can therefore be tolerated in "low power" circuits too.
Since this resistor R1 is however--as stated above--usually formed by a p-well resistor, and its surface resistance is only about 2 k.OMEGA. for technological reasons, a disproportionately large chip area (approx. 1 mm.sup.2) would be required for a resistance of that magnitude, which is of course also undesirable.
Finally, there is the possibility of reducing the current input by using a high-value resistor R1 in the form of a specially generated layer, for example implanted polysilicon with high surface resistance and hence low space requirement. The provision of a high-value polyresistor of this type does however require a special mask and also additional process steps, and thus causes increased costs. A resistor of this type can also only be manufactured with relatively wide tolerances, so that the current i3 tappable via the transistor T5 is also subject to heavy dispersion, and the circuit is not suitable for applications in which the current i3 should remain largely constant.